Datasheet

Section 21 Mask ROM
Rev.6.00 Mar. 18, 2009 Page 811 of 980
REJ09B0050-0600
Section 21 Mask ROM
H8S/2635 has 256 kbytes of mask ROM. The on-chip ROM is connected to the CPU, data transfer
controller (DTC), and DMA controller (DMAC) with a 16-bit data bus. The on-chip ROM can be
accessed by the CPU, DTC, and DMAC in 8 or 16-bit units. The data in the on-chip ROM can
always be accessed in one state.
H'000000
H'000002
H'03FFFE
H'000001
H'000003
H'03FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 21.1 Block Diagram of 256-kbyte Mask ROM (HD6432365)
The on-chip ROM is enabled or disabled according to the operating mode. The operating mode is
selected by the mode setting pins MD2 to MD0 as shown in table 3.1. Select mode 4 or 7 when the
on-chip ROM is used, and mode 1 or 2 when the on-chip ROM is not used. The on-chip ROM is
allocated in area 0.