Datasheet

Section 20 Flash Memory (0.18-μm F-ZTAT Version)
Rev.6.00 Mar. 18, 2009 Page 780 of 980
REJ09B0050-0600
The FLER bit is set in the following conditions:
1. When an interrupt such as NMI occurs during programming/erasing.
2. When the flash memory is read during programming/erasing (including a vector read or an
instruction fetch).
3. When a SLEEP instruction (including software-standby mode) is executed during
programming/erasing.
4. When a bus master other than the CPU such as the DMAC or DTC gets bus mastership during
programming/erasing.
Error protection is cancelled only by a power-on reset or by hardware-standby mode. Note that the
reset should only be released after providing a reset input over a period longer than the normal 100
μs period. Since high voltages are applied during programming/erasing of the flash memory, some
voltage may remain after the error-protection state has been entered. For this reason, it is
necessary to reduce the risk of damage to the flash memory by extending the reset period so that
the charge is released.
The state-transition diagram in figure 20.15 shows transitions to and from the error-protection
state.
Reset or standby
(Hardware protection)
Program mode
Erase mode
Error protection mode
Error-protection mode
(Software standby)
Read disabled
Programming/erasing
enabled
FLER = 0
Read disabled
Programming/erasing disabled
FLER = 0
Read enabled
Programming/erasing disabled
FLER = 1
Read disabled
programming/erasing disabled
FLER = 1
RES = 0 or STBY = 0
Error occurrence
Error occurred
(Software standby)
RES = 0 or
STBY = 0
Software-standby mode
Cancel
software-standby mode
RES = 0 or
STBY = 0
Program/erase interface
register is in its initial state.
Program/erase interface
register is in its initial state.
Figure 20.15 Transitions to Error-Protection State