Datasheet

Section 2 CPU
Rev.6.00 Mar. 18, 2009 Page 22 of 980
REJ09B0050-0600
⎯ 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
⎯ 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
• Two CPU operating modes
⎯ Normal mode
*
⎯ Advanced mode
Note: * For this LSI, normal mode is not available.
• Power-down state
⎯ Transition to power-down state by SLEEP instruction
⎯ Selectable CPU clock speed
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs, Rd 3 12
MULXU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 13
MULXS.W Rs, ERd 5 21
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.