Datasheet

Section 20 Flash Memory (0.18-μm F-ZTAT Version)
Rev.6.00 Mar. 18, 2009 Page 750 of 980
REJ09B0050-0600
Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI
Bit Rate of Host System Clock Frequency
9,600 bps 8 to 25 MHz
19,200 bps 8 to 25 MHz
(2) State Transition Diagram
The overview of the state transition diagram after boot mode is initiated is shown in figure 20.8.
1. Bit rate adjustment
After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host.
2. Waiting for inquiry set command
For inquiries about user-MAT size and configuration, MAT start address, and support state,
the required information is transmitted to the host.
3. Automatic erasure of all user MAT and user boot MAT
After inquiries have finished, all user MAT and user boot MAT are automatically erased.
4. Waiting for programming/erasing command
⎯ When the program preparation notice is received, the state for waiting program data is
entered. The programming start address and program data must be transmitted following
the programming command. When programming is finished, the programming start address
must be set to H'FFFFFFFF and transmitted. Then the state for waiting program data is
returned to the state of programming/erasing command wait. Before reprogramming erased
blocks containing a programming finished area for which the programming finished
command has been issued, make sure to erase the corresponding erased blocks.
:
EB9
EB10
EB11
EB12
:
Before reprogramming erased blocks containing a programming
finished area (EB10 and EB11), the corresponding erased
blocks (EB10 and EB11) should be erased.
Programming finished area