Datasheet

Section 20 Flash Memory (0.18-μm F-ZTAT Version)
Rev.6.00 Mar. 18, 2009 Page 736 of 980
REJ09B0050-0600
Table 20.4 Parameters and Target Modes
Name of
Parameter
Abbrevia-
tion
Down
Load
Initializa-
tion
Program-
ming
Erasure R/W
Initial
Value
Alloca-
tion
Download pass
and fail result
DPFR
⎯ ⎯ ⎯
R/W Undefined
On-chip
RAM*
Flash pass and fail
result
FPFR R/W Undefined R0L of
CPU
Flash
programming/
erasing frequency
control
FPEFEQ
⎯ ⎯ ⎯ R/W Undefined ER0 of
CPU
Flash user branch
address set
FUBRA ⎯ ⎯ ⎯ R/W Undefined ER1 of
CPU
Flash multipurpose
address area
FMPAR ⎯ ⎯ ⎯ R/W Undefined ER1 of
CPU
Flash multipurpose
data destination
area
FMPDR
⎯ ⎯ ⎯ R/W Undefined ER0 of
CPU
Flash erase block
select
FEBS ⎯ ⎯ ⎯ R/W Undefined R0L of
CPU
Note: * A single byte of the start address to download an on-chip program, which is specified by
FTDAR.
(1) Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip RAM
area to be downloaded is the 128-kbyte area starting from the address specified by FTDAR.
Download control is set in the program/erase interface register, and the return value is passed
using the DPFR parameter.
(a) Download pass/fail result parameter (DPFR: single byte of start address specified by FTDAR)
This parameter indicates the return value of the download result. The value of this parameter can
be used to determine if downloading is executed or not. Since the confirmation whether the SCO
bit is set to 1 is difficult, the certain determination must be performed by writing the single byte of
the start address specified by FTDAR to the value other than the return value of download (for
example, H'FF) before the download start (before setting the SCO bit to 1).