Datasheet

Section 20 Flash Memory (0.18-μm F-ZTAT Version)
Rev.6.00 Mar. 18, 2009 Page 728 of 980
REJ09B0050-0600
20.3.1 Programming/Erasing Interface Register
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a
power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not
initialized in software standby mode.
• Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error
occurrence during programming or erasing flash memory and the download of on-chip
program.
Bit Bit Name
Initial
Value R/W Description
7 ⎯ 1 R Reserved
This bit is always read as 0. The write value should
always be 1.
6, 5 ⎯ All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.