Datasheet

Section 20 Flash Memory (0.18-μm F-ZTAT Version)
Rev.6.00 Mar. 18, 2009 Page 726 of 980
REJ09B0050-0600
20.2 Input/Output Pins
Table 20.2 shows the flash memory pin configuration.
Table 20.2 Pin Configuration
Pin Name Abbreviation Input/Output Function
Reset RES Input Reset
Mode 2 MD2 Input Sets operating mode of this LSI
Mode 1 MD1 Input Sets operating mode of this LSI
Mode 0 MD0 Input Sets operating mode of this LSI
Port 52 P52 Input Sets operating mode of programmer
mode
Port 51 P51 Input Sets operating mode of programmer
mode
Port 50 P50 Input Sets operating mode of programmer
mode
Transmit data TxD1 Output Serial transmit data output (used in boot
mode)
Receive data RxD1 Input Serial receive data input (used in boot
mode)
Note: For the pin configuration in PROM mode, see section 20.7, Programmer Mode.
20.3 Register Descriptions
The registers/parameters which control flash memory are shown as follows.
• Flash code control status register (FCCS)
• Flash program code select register (FPCS)
• Flash erase code select register (FECS)
• Flash key code register (FKEY)
• Flash MAT select register (FMATS)
• Flash transfer destination address register (FTDAR)
• Download pass and fail result (DPFP)
• Flash pass and fail result (FPFR)
• Flash multipurpose address area (FMPAR)
• Flash multipurpose data destination area (FMPDR)
• Flash erase Block select (FEBS)