Datasheet

Section 1 Overview
Rev.6.00 Mar. 18, 2009 Page 16 of 980
REJ09B0050-0600
Pin No.
Type Symbol
TFP-120 QFP-128
*
1
I/O Function
Bus control BACK 107 117 Output Indicates the bus is released to the
external bus master.
UCAS 70 78 Output Upper column address strobe
signal for accessing the 16-bit
DRAM space.
Column address strobe signal for
accessing the 8-bit DRAM space.
LCAS 71 79 Output Lower column address strobe
signal for accessing the 16-bit
DRAM space.
RAS2
RAS3
91
92
101
102
Output Row address strobe signal for the
DRAM interface.
WAIT 69 77 Input Requests insertion of a wait state in
the bus cycle when accessing
external 3-state address space.
OE
(OE)
69,
113
77,
123
Output Output enable signal for accessing
the DRAM space.
The output pins of OE and (OE) are
selected by the port function control
register 2 (PFCR2) of port 3.
NMI 32 38 Input Nonmaskable interrupt request pin.
Fix high when not used.
Interrupt
signals
IRQ7 to
IRQ0
(IRQ7) to
(IRQ0)
29 to 26,
112 to 109,
102 to 95
33 to 30,
122 to 119,
112 to 105
Input These pins request a maskable
interrupt.
The input pins of IRQn and (IRQn)
are selected by the IRQ pin select
register (ITSR) of the interrupt
controller. (n = 0 to 7)
DMA controller
(DMAC)
DREQ1
DREQ0
35,
34
41,
40
Input These signals request DMAC
activation.
TEND1,
TEND0
37,
36
43,
42
Output These signals indicate the end of
DMAC data transfer.
DACK1,
DACK0
39,
38
45,
44
Output DMAC single address transfer
acknowledge signals.