Datasheet

Section 19 Flash Memory (0.35-μm F-ZTAT Version)
Rev.6.00 Mar. 18, 2009 Page 697 of 980
REJ09B0050-0600
19.4 Input/Output Pins
The flash memory is controlled by means of the pins shown in table 19.2.
Table 19.2 Pin Configuration
Pin Name I/O Function
RES Input Reset
MD2 Input Sets this LSI’s operating mode
MD1 Input Sets this LSI’s operating mode
MD0 Input Sets this LSI’s operating mode
P52 Input Sets operating mode in programmer mode
P51 Input Sets operating mode in programmer mode
P50 Input Sets operating mode in programmer mode
TxD1 Output Serial transmit data output
RxD1 Input Serial receive data input
19.5 Register Descriptions
The flash memory has the following registers. For details on the system control register, refer to
section 3.2.2, System Control Register (SYSCR).
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)