Datasheet

Section 1 Overview
Rev.6.00 Mar. 18, 2009 Page 15 of 980
REJ09B0050-0600
Pin No.
Type Symbol
TFP-120 QFP-128
*
1
I/O Function
System control RES 77 85 Input Reset pin. When this pin is driven
low, the chip is reset.
STBY 88 96 Input When this pin is driven low, a
transition is made to hardware
standby mode.
EMLE 30 34 Input Enables emulator. This pin should
be connected to the power supply
(0 V).
Address bus A23 to
A0
29 to 23,
21 to 18,
16 to 9,
7 to 3
33 to 27,
25 to 22,
20 to 13,
11 to 7
Output Address output pins.
Data bus D15 to
D0
68 to 61,
59,
57 to 51
76 to 69,
65,
63 to 57
Input/
output
These pins constitute a bidirectional
data bus.
Bus control CS7 to
CS0
29,71,70,
106,
92 to 89
33,79,78,
116,102,
101,98,97
Output Signals that select division areas 7
to 0 in the external address space.
AS 75 83 Output When this pin is low, it indicates
that address output on the address
bus is valid.
RD 74 82 Output When this pin is low, it indicates
that the external address space is
being read.
HWR 73 81 Output Strobe signal indicating that
external address space is to be
written, and the upper half (D15 to
D8) of the data bus is enabled.
Write enable signal for accessing
the DRAM space.
LWR 72 80 Output Strobe signal indicating that
external address space is to be
written, and the lower half (D7 to
D0) of the data bus is enabled.
BREQ 108 118 Input The external bus master requests
the bus to this LSI.
BREQO 106 116 Input External bus request signal when
the internal bus master accesses
the external space in external bus
release state.