Datasheet

Section 16 A/D Converter
Rev.6.00 Mar. 18, 2009 Page 671 of 980
REJ09B0050-0600
(1)
(2)
t
D
t
SPL
t
CONV
φ
Address
Write signal
Input sampling
timing
ADF
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 16.2 A/D Conversion Timing