Datasheet

Section 16 A/D Converter
Rev.6.00 Mar. 18, 2009 Page 669 of 980
REJ09B0050-0600
16.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
16.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software
or external trigger input.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion
stops and the A/D converter enters wait state.
16.4.2 Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels:
maximum four channels or maximum eight channels. Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by software, TPU or external trigger input, A/D
conversion starts on the first channel in the group.
The consecutive A/D conversion on maximum four channels (SCANE and SCANS = 10) or on
maximum eight channels (SCANE and SCANS = 11) can be selected. When the consecutive
A/D conversion is performed on the four channels, the A/D conversion starts on AN0 when
CH3 = 1 and CH2 = 1, AN4 when CH3 and CH2 = 01, or AN12 when CH3 and CH2 = 11.
When the consecutive A/D conversion is performed on the eight channels, the A/D conversion
starts on AN0 when CH3 = 0.
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the corresponding A/D data register to each channel.