Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 659 of 980
REJ09B0050-0600
SCL
VIH
SCL monitor
timing reference
clock
Internal SCL
Figure 15.18 Timing of the Bit Synchronous Circuit
Table 15.4 Time for monitoring SCL
CKS3 CKS2 Time for monitoring SCL
0 7.5 tcyc
*
0
1 19.5 tcyc
1 0 17.5 tcyc
1 41.5 tcyc
Note: * If the operating frequency exceeds 20 MHz, it may not be possible to maintain the
prescribed transfer rate under certain load conditions. A setting other than 7.5 tcyc
should therefore be used.
15.7 Usage Notes
1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed.
Check SCLO in the I
2
C control register B (ICCRB)* to confirm the fall of the ninth clock.
When the start/stop conditions are issued (retransmitted) at the specific timing under the
following condition (i) or (ii), such conditions may not be output successfully. This does not
occur in other cases.
(i) When the rising of SCL falls behind the time specified in section 15.6, Bit Synchronous
Circuit, by the load of the SCL bus (load capacitance or pull-up resistance)
(ii) When the bit synchronous circuit is activated by extending the low period of eighth and
ninth clocks, that is driven by the slave device
2. Control WAIT in the I
2
C bus mode register (ICMR) to be set to 0.
When WAIT is set to 1, and SCL is driven low for two or more transfer clocks by the slave
device at the eighth and ninth clocks, the high period of ninth clock may be shortened. This
does not occur in other cases.