Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 658 of 980
REJ09B0050-0600
15.5 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost. Table 15.3 shows the contents of each
interrupt request.
Table 15.3 Interrupt Requests
Interrupt Request Abbreviation Interrupt Condition
Transmit Data Empty TXI (TDRE = 1)
•
(TIE = 1)
Transmit End TEI (TEND = 1)
•
(TEIE = 1)
Receive Data Full RXI (RDRF = 1)
•
(RIE = 1)
STOP Recognition STPI (STOP = 1)
•
(STIE = 1)
NACK Detection NAKI {(NACKF = 1)+(AL = 1)}
•
(NAKIE = 1)
Arbitration Lost
When interrupt conditions described in table 15.3 are 1 and the CPU is ready to receive interrupts,
an interrupt execution handling is executed. Clear each interrupt source during an interrupt
execution handling. Note that TDRE and TEND are automatically cleared by writing the transmit
data to ICDRT, and RDRF is automatically cleared by reading ICDRR. When the transmit data is
written to ICDRT, TDRE is set again simultaneously. When TDRE is cleared, extra one byte of
data may be transmitted.
15.6 Bit Synchronous Circuit
In master mode,
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up
resistance)
This module has a possibility that high level period may be short in the two states described
above. Therefore it monitors SCL and communicates by bit with synchronization.
Figure 15.18 shows the timing of the bit synchronous circuit and table 15.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.