Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 654 of 980
REJ09B0050-0600
BBSY=0 ?
No
TEND=1 ?
No
Yes
Start
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[13]
[14]
[15]
Initialize
Set MST = 1 and TRS
= 1 in ICCRA.
Write BBSY = 1
and SCP = 0.
Write transmit data
in ICDRT
Write BBSY = 0
and SCP = 0
Set MST = 1 and TRS
= 0 in ICCRA
Read BBSY in ICCRB
Read TEND in ICSR
Read ACKBR in ICIER
Master receive mode
Yes
ACKBR=0 ?
Write transmit data in ICDRT
Read TDRE in ICSR
Read TEND in ICSR
Clear TEND in ICSR
Read STOP in ICSR
Clear TDRE in ICSR
End
Write transmit data in ICDRT
Transmit
mode?
No
Yes
TDRE=1 ?
Final byte?
STOP=1 ?
No
No
No
No
No
Yes
Yes
TEND=1 ?
Yes
Yes
Yes
[1] Test the status of the SCL and SDA lines.*
[2] Select master transmit mode.*
[3] Start condition issuance.*
[4] Select transmit data for the first byte (slave address + R/W),
and clear TDRE to 0.
[5] Wait for 1 byte to be transmitted.
[6] Test the acknowledge bit, transferred from the specified slave device.
[7] Set transmit data for the second and subsequent data (except for the final byte),
and clear TDRE and TEND to 0.
[8] Wait for ICDRT empty.
[9] Set the final byte of transmit data, and clear TDRE and TEND to 0.
[10] Wait for the completion of transmission for the final byte.
[11] Clear TEND flag.
[12] Clear STOP flag.
[13] Stop condition issuance.
[14] Wait for the creation of the stop condition.
[15] Set slave receive mode. Clear TDRE.
[12]
Clear STOP in ICSR
Note: * Ensure that no interrupts occur between
when BBSY is cleared to 0 and start condition [3].
Figure 15.14 Sample Flowchart for Master Transmit Mode