Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 653 of 980
REJ09B0050-0600
15.4.6 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
C
QD
March detector
Internal
SCL or SDA
signal
SCL or SDA
input signal
Sampling
clock
Sampling clock
System clock
period
Latch Latch
C
QD
Figure 15.13 Block Diagram of Noise Canceler
15.4.7 Example of Use
Flowcharts in respective modes that use the I
2
C bus interface are shown in figures 15.14 to 15.17.