Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 651 of 980
REJ09B0050-0600
3. Clear RDRF after reading ICDRR every time RDRF is set. If 8th receive clock pulse falls
while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge
before reading ICDRR, to be returned to the master device, is reflected to the next transmit
frame.
4. The last byte data is read by reading ICDRR.
ICDRS
ICDRR
12 1345678 99
AA
RDRF
Data 1 Data 2
Data 1
SCL
(master output)
SDA
(master output)
SDA
(slave output)
SCL
(slave output)
Bit 7 Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[2] Read ICDRR (dummy read), and clear RDRF.
[2] Read ICDRR, and clear RDRF.
User
processing
Figure 15.11 Slave Receive Mode Operation Timing 1