Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 647 of 980
REJ09B0050-0600
7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RDRF to 0. Then clear the
RCVD bit to 0.
8. The operation returns to the slave receive mode.
TDRE
TEND
ICDRS
ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
[3] Read ICDRR
1
A
2134567899
A
TRS
RDRF
SCL
(master output)
SDA
(master output)
SDA
(slave output)
Bit 7
Master transmit mode Master receive mode
Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
User
processing
Data 1
Data 1
Figure 15.7 Master Receive Mode Operation Timing 1