Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 645 of 980
REJ09B0050-0600
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
TDRE
SCL
(master output)
SDA
(master output)
SDA
(slave output)
TEND
[5] Write data to ICDRT (third byte).
Clear TDRE.
ICDRT
ICDRS
[2] Instruction of start
condition issuance
[3] Write data to ICDRT (first byte).
Clear TDRE.
[4] Write data to ICDRT (second byte).
Clear TDRE and TEND.
User
processing
1
Bit 7
Slave address
Address + R/
Data 1
Data 1
Data 2
Address + R/
Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2123456789
A
R/
Figure 15.5 Master Transmit Mode Operation Timing 1