Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 639 of 980
REJ09B0050-0600
15.3.5 I
2
C Bus Status Register (ICSR)
ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
Bit Bit Name Initial Value R/W Description
7 TDRE 0 R/W Transmit Data Register Empty
[Setting conditions]
• When data is transferred from ICDRT to ICDRS and
ICDRT becomes empty
• When TRS is set
• When a transition from receive mode to transmit mode is
made in slave mode
[Clearing conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When data is written to ICDRT
6 TEND 0 R/W Transmit end
[Setting condition]
When the ninth clock of SCL is rose while the TDRE flag is
1
[Clearing conditions]
• When 0 is written in TEND after reading TEND = 1
• When data is written to ICDRT
5 RDRF 0 R/W Receive Data Register Full
[Setting condition]
When a received data is transferred from ICDRS to ICDRR
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When ICDRR is read