Datasheet

Section 15 I

C Bus Interface2 (IIC2) (Option)

Rev.6.00 Mar. 18, 2009 Page 636 of 980

REJ09B0050-0600

Bit Bit Name Initial Value R/W Description

0 ⎯ 1 ⎯ Reserved

This bit is always read as 1.

15.3.3 I

C Bus Mode Register (ICMR)

ICMR performs master mode wait control and selects the transfer bit count.

Bit Bit Name Initial Value R/W Description

7 ⎯ 0 R/W Reserved

The write value should always be 0.

6 WAIT 0 R/W Wait Insertion Bit

This bit selects whether to insert a wait after data transfer

except for the acknowledge bit. When WAIT is set to 1,

after the fall of the clock for the final data bit, low period is

extended for two transfer clocks. If WAIT is cleared to 0,

data and acknowledge bits are transferred consecutively

with no wait inserted.

The setting of this bit is invalid in slave mode.

5, 4 ⎯ All 1 ⎯ Reserved

These bits are always read as 1.

3 BCWP 1 R/W BC Write Protect

This bit controls the BC2 to BC0 modifications. When

modifying BC2 to BC0, this bit should be cleared to 0 and

use the MOV instruction.

0: When writing, values of BC2 to BC0 are set.

1: When reading, 1 is always read.

When writing, settings of BC2 to BC0 are invalid.