Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 120 (14x14) 16-Bit 34 MHz I/O number 83

Section 15 I

2

C Bus Interface2 (IIC2) (Option)

Rev.6.00 Mar. 18, 2009 Page 630 of 980

REJ09B0050-0600

SCL

ICCRA

Transfer clock

generation

circuit

Address

comparator

Interrupt

generator

Interrupt request

Bus state

decision circuit

Arbitration

decision circuit

Noise canceler

Noise canceler

Output

control

Output

control

Transmission/

reception

control circuit

ICCRB

ICMR

ICSR

ICEIR

ICDRR

ICDRS

ICDRT

I

2

C bus control register A

I

2

C bus control register B

I

2

C mode register

I

2

C status register

I

2

C interrupt permission register

I

2

C transmission data register

I

2

C reception data register

I

2

C bus shift register

Slave address register

Legend:

ICCRA:

ICCRB:

ICMR:

ICSR:

ICIER:

ICDRT:

ICDRR:

ICDRS:

SAR:

SAR

SDA

Internal data bus

Figure 15.1 Block Diagram of I

2

C Bus Interface2