Datasheet

Section 15 I
2
C Bus Interface2 (IIC2) (Option)
Rev.6.00 Mar. 18, 2009 Page 629 of 980
REJ09B0050-0600
Section 15 I
2
C Bus Interface2 (IIC2) (Option)
An I
2
C bus interface is an option. When using the optional functions, take notice of the following
item:
For the masked ROM version, ‘W’ is added to the model name of the product that uses optional
functions.
For example: HD6432365WTE
This LSI has a two-channel I
2
C bus interface,
The I
2
C bus interface conforms to and provides a subset of the NXP Semiconductors I
2
C bus
(inter-IC bus) interface (Rev.03) standard and fast mode functions. The register configuration that
controls the I
2
C bus differs partly from the NXP Semiconductors configuration, however.
Figure 15.1 shows a block diagram of the I
2
C bus interface2.
Figure 15.2 shows an example of I/O pin connections to external circuits.
15.1 Features
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
• Six interrupt sources
⎯ Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
• Direct bus drive
⎯ Two pins, SCL and SDA pins function as NMOS open-drain outputs.
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