Datasheet

Section 14 Serial Communication Interface (SCI, IrDA)
Rev.6.00 Mar. 18, 2009 Page 617 of 980
REJ09B0050-0600
In the specification, the high pulse width is fixed at a minimum of 1.41 µs, and a maximum of
(3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can
be set for a high pulse width with a minimum value of 1.41 µs.
When the serial data is 1, no pulse is output.
UART frame
Data
IR frame
Data
0000 011 111
0000 011 111
Start
bit
Transmit Receive
Stop
bit
Start
bit
Stop
bit
Bit
cycle
Pulse width
1.6 μs to 3/16 bit cycle
Figure 14.34 IrDA Transmit/Receive Operations
Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and
input to the SCI.
When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1
data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will be identified
as a 0 signal.
High Pulse Width Selection: Table 14.12 shows possible settings for bits IrCKS2 to IrCKS0
(minimum pulse width), and operating frequencies of this LSI and bit rates, for making the pulse
width shorter than 3/16 times the bit rate in transmission.