Datasheet

Section 1 Overview
Rev.6.00 Mar. 18, 2009 Page 4 of 980
REJ09B0050-0600
PE7/D7 PE6/D6 PE5/D5 PE4/D4 PE3/D3 PE2/D2 PE1/D1 PE0/D0 PD7/D15 PD6/D14 PD5/D13 PD4/D12 PD3/D11 PD2/D10 PD1/D9 PD0/D8
V
CC
V
CC
V
CC
V
CC
PLLV
CC
PLLV
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3/A11
PB2/A10
PB1/A9
PB0/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
P47/AN7/(IRQ7)
P46/AN6/(IRQ6)
P45/AN5/(IRQ5)
P44/AN4/(IRQ4)
P43/AN3/(IRQ3)
P42/AN2/(IRQ2)
P41/AN1/(IRQ1)
P40/AN0/(IRQ0)
Vref AV
CC
AV
SS
P10/PO8/TIOCA0/DREQ0 P11/PO9/TIOCB0/DREQ1
P12/PO10/TIOCC0/TCLKA/TEND0 P13/PO11/TIOCD0/TCLKB/TEND1
P14/PO12/TIOCA1/DACK0
P15/PO13/TIOCB1/TCLKC/DACK1
P16/PO14/TIOCA2
P17/PO15/TIOCB2/TCLKD
P85/SCK3
P83/RxD3
P81/TxD3
PG6/BREQ
PG5/BACK
PG4/CS4/BREQO
PG3/CS3/RAS3
PG2/CS2/RAS2
PG1/CS1
PG0/CS0
PF7/ φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2/CS6/LCAS
PF1
/ CS5/UCAS
PF0/WAIT/OE
RAM
WDT
H8S/2000 CPU
DTC
DMAC
PLL
PA7/A23/CS7/IRQ7
PA6/A22/IRQ6
PA5/A21/IRQ5
PA4/A20/IRQ4
PA3/A19
PA2/A18
PA1/A17
PA0/A16
P20/PO0/TIOCA3/TMRI0 P21/PO1/TIOCB3/TMRI1
P22/PO2/TIOCC3/TMCI0
P23/PO3/TIOCD3/TxD4/TMCI1
P24/PO4/TIOCA4/RxD4/TMO0
P25/PO5/TIOCB4/TMO1
P26/PO6/TIOCA5 P27/PO7/TIOCB5
MD2
MD1
MD0
EXTAL
XTAL
EMLE
STBY
RES
WDTOVF
NMI
P95/AN13/DA3 P94/AN12/DA2
P35/SCK1/SCL0/(OE)
P34/SCK0/SCK4/SDA0
P33/RxD1/SCL1
P32/RxD0/IrRxD/SDA1
P31/TxD1
P30/TxD0/IrTxD
P53/ADTRG//IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Port D Port E
Port 1 Port 2 Port 4 Port 9
Port APort BPort CPort 5 Port 3
Port FPort GPort 8
Clock
pulse
generator
Interrupt controller
ROM
(Flash memory)
TPU × 6 channels
PPG
TMR × 2 channels
SCI × 5 channels
I
2
C bus interface 2 (option)
8-bit D/A converter
10-bit A/D converter
Bus controller
Internal data bus
Internal address bus
Peripheral data bus
Peripheral address bus
V
CL
Figure 1.2 Internal Block Diagram of H8S/2368 0.18 μm F-ZTAT Group