Datasheet

Section 14 Serial Communication Interface (SCI, IrDA)
Rev.6.00 Mar. 18, 2009 Page 541 of 980
REJ09B0050-0600
Section 14 Serial Communication Interface (SCI, IrDA)
This LSI has five independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. Serial data communication
can be carried out with standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A function is also provided for serial communication between processors
(multiprocessor communication function) in asynchronous mode. The SCI also supports an IC
card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as an
asynchronous serial communication interface extension function. One of the five SCI channels
(SCI_0) can generate an IrDA communication waveform conforming to IrDA specification
version 1.0.
Figure 14.1 shows a block diagram of the SCI.
14.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source (except for in Smart Card interface
mode).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive
error — that can issue requests. The transmit-data-empty interrupt and receive data full
interrupts can activate the data transfer controller (DTC) or DMA controller (DMAC).
• Module stop mode can be set
Asynchronous mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
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