Datasheet

Section 13 Watchdog Timer
Rev.6.00 Mar. 18, 2009 Page 537 of 980
REJ09B0050-0600
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 13.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte
data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer
instruction cannot perform writing to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0
to the WOVF bit, satisfy the lower condition shown in figure 13.4.
If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit.
To write to the RSTE bit, satisfy the above condition shown in figure 13.4. If satisfied, the transfer
instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the
WOVF bit.
TCNT write or
Writing to RSTE bit in RSTCSR
TCSR write
Address: H'FFBC (TCNT)
H'FFBE (RSTCSR)
15 8 7 0
H'5A Write data
Address: H'FFBC (TCSR)
15 8 7 0
H'A5 Write data
Writing 0 to WOVF bit in RSTCSR
Address: H'FFBE (RSTCSR)
15 8 7 0
H'A5 H'00
Figure 13.4 Writing to TCNT, TCSR, and RSTCSR
Reading TCNT, TCSR, and RSTCSR
These registers are read in the same way as other registers. The read addresses are H'FFBC for
TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.