Datasheet

Section 13 Watchdog Timer
Rev.6.00 Mar. 18, 2009 Page 531 of 980
REJ09B0050-0600
13.3 Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to in a method different from normal registers. For details, refer to
section 13.6.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
13.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
TCSR is cleared to 0.
13.3.2 Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit Bit Name Initial Value R/W Description
7 OVF 0 R/(W)
*
Overflow Flag
Indicates that TCNT has overflowed in interval
timer mode. Only a write of 0 is permitted, to
clear the flag.
[Setting condition]
When TCNT overflows in interval timer mode
(changes from H’FF to H’00)
When internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF