Datasheet

Section 12 8-Bit Timers (TMR)
Rev.6.00 Mar. 18, 2009 Page 524 of 980
REJ09B0050-0600
12.8.3 Contention between TCOR Write and Compare Match
During the T
2
state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs as shown in figure 12.12.
φ
Address
TCOR address
Internal write signal
TCNT
TCOR
NM
T
1
T
2
TCOR write cycle by CPU
TCOR write data
N N+1
Compare match signal
Inhibited
Figure 12.12 Contention between TCOR Write and Compare Match