Datasheet

Section 12 8-Bit Timers (TMR)
Rev.6.00 Mar. 18, 2009 Page 523 of 980
REJ09B0050-0600
12.8.2 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 12.11 shows this operation.
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
NM
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 12.11 Contention between TCNT Write and Increment