Datasheet

Section 12 8-Bit Timers (TMR)
Rev.6.00 Mar. 18, 2009 Page 519 of 980
REJ09B0050-0600
12.5.5 Timing of TCNT External Reset
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12.8
shows the timing of this operation.
φ
Clear signal
External reset
input pin
TCNT N H'00N–1
Figure 12.8 Timing of Clearance by External Reset
12.5.6 Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.9
shows the timing of this operation.
φ
OVF
Overflow signal
TCNT H'FF H'00
Figure 12.9 Timing of OVF Setting