Datasheet

Section 12 8-Bit Timers (TMR)
Rev.6.00 Mar. 18, 2009 Page 516 of 980
REJ09B0050-0600
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 12.2 Example of Pulse Output
12.5 Operation Timing
12.5.1 TCNT Incrementation Timing
Figure 12.3 shows the count timing for internal clock input. Figure 12.4 shows the count timing
for external clock signal. Note that the external clock pulse width must be at least 1.5 states for
incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The
counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
Clock input
to TCNT
TCNT
N–1 N N+1
Figure 12.3 Count Timing for Internal Clock Input