Datasheet

Section 12 8-Bit Timers (TMR)
Rev.6.00 Mar. 18, 2009 Page 512 of 980
REJ09B0050-0600
Table 12.2 Clock Input to TCNT and Count Condition
TCR
Channel Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0 Description
TMR_0 0 0 0 Clock input disabled
1 Internal clock, counted at falling edge of φ/8
1 0 Internal clock, counted at falling edge of φ/64
1 Internal clock, counted at falling edge of φ/8192
1 0 0 Count at TCNT_1 overflow signal
*
TMR_1 0 0 0 Clock input disabled
1 Internal clock, counted at falling edge of φ/8
1 0 Internal clock, counted at falling edge of φ/64
1 Internal clock, counted at falling edge of φ/8192
1 0 0 Count at TCNT_0 compare match A
*
All 1 0 1 External clock, counted at rising edge
1 0 External clock, counted at falling edge
1 1 External clock, counted at both rising and falling edges
Note: * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
12.3.5 Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output.
TCSR_0
Bit Bit Name Initial Value R/W Description
7 CMFB 0 R/(W)
*
Compare Match Flag B
[Setting condition]
Set when TCNT matches TCORB
[Clearing conditions]
• Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
• When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0