Datasheet

Section 12 8-Bit Timers (TMR)
Rev.6.00 Mar. 18, 2009 Page 508 of 980
REJ09B0050-0600
Figure 12.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
External clock source Internal clock sources
TMR_0
φ/8
φ/64
φ/8192
TMR_1
φ/8
φ/64
φ/8192
Clock 1
Clock 0
Compare match A1
Compare match A0
Clear 1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
TCORA_0: Time constant register A_0
TCORB_0: Time constant register B_0
TCNT_0: Timer counter_0
TCSR_0: Timer control/status register_0
TCR_0: Timer control register_0
TCORA_1: Time constant register A_1
TCORB_1: Time constant register B_1
TCNT_1: Timer counter_1
TCSR_1: Timer control/status register_1
TCR_1: Timer control register_1
TMO0
TMRI0
Internal bus
TCORA_0
Comparator A_0
Comparator B_0
TCORB_0
TCSR_0
TCR_0
TCORA_1
Comparator A_1
TCNT_1
Comparator B_1
TCORB_1
TCSR_1
TCR_1
TMCI0
TMCI1
TCNT_0
Overflow 1
Overflow 0
Compare match B1
Compare match B0
TMO1
TMRI1
A/D
conversion
start request
signal
Clock select
Control logic
Clear 0
Legend:
Figure 12.1 Block Diagram of 8-Bit Timer Module