Datasheet

Rev.6.00 Mar. 18, 2009 Page liv of lviii

REJ09B0050-0600

Section 11 Programmable Pulse Generator (PPG)

Table 11.1

Pin Configuration ................................................................................................... 487

Section 12 8-Bit Timers (TMR)

Table 12.1

Pin Configuration ................................................................................................... 509

Table 12.2 Clock Input to TCNT and Count Condition ........................................................... 512

Table 12.3 8-Bit Timer Interrupt Sources ................................................................................ 521

Table 12.4 Timer Output Priorities .......................................................................................... 525

Table 12.5 Switching of Internal Clock and TCNT Operation ................................................ 526

Section 13 Watchdog Timer

Table 13.1

Pin Configuration ................................................................................................... 530

Table 13.2 WDT Interrupt Source............................................................................................ 536

Section 14 Serial Communication Interface (SCI, IrDA)

Table 14.1 Pin Configuration ................................................................................................... 544

Table 14.2 Relationships between N Setting in BRR and Bit Rate B ...................................... 564

Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) .................................. 565

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................ 567

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. 568

Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ...................... 569

Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... 570

Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)

(when n = 0 and S = 372) ....................................................................................... 571

Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(when S = 372)....................................................................................................... 572

Table 14.10 Serial Transfer Formats (Asynchronous Mode) ..................................................... 577

Table 14.11 SSR Status Flags and Receive Data Handling........................................................ 585

Table 14.12 Settings of Bits IrCKS2 to IrCKS0 ........................................................................ 618

Table 14.13 SCI Interrupt Sources............................................................................................. 620

Table 14.14 Interrupt Sources .................................................................................................... 621

Section 15 I

C Bus Interface2 (IIC2) (Option)

Table 15.1 Pin Configuration ................................................................................................... 631

Table 15.2 Transfer Rate.......................................................................................................... 634

Table 15.3 Interrupt Requests .................................................................................................. 658

Table 15.4 Time for monitoring SCL....................................................................................... 659

Section 16 A/D Converter

Table 16.1 Pin Configuration ................................................................................................... 663