Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 483 of 980
REJ09B0050-0600
Input capture
signal
Write signal
Address
φ
TCNT
Buffer register write cycle
T
1
T
2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 10.51 Contention between Buffer Register Write and Input Capture
10.10.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
Counter
clearing signal
TCNT input
clock
φ
TCNT
TGF
Disabled
TCFV
H'FFFF H'0000
Figure 10.52 Contention between Overflow and Counter Clearing