Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 482 of 980
REJ09B0050-0600
10.10.9 Contention between TGR Write and Input Capture
If the input capture signal is generated in the T
2
state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
TGR write cycle
T
1
T
2
M
TGR
M
TGR address
Figure 10.50 Contention between TGR Write and Input Capture
10.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T
2
state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 10.51 shows the timing in this case.