Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 481 of 980
REJ09B0050-0600
10.10.8 Contention between TGR Read and Input Capture
If the input capture signal is generated in the T
1
state of a TGR read cycle, the data that is read will
be the data after input capture transfer.
Figure 10.49 shows the timing in this case.
Input capture
signal
Read signal
Address
φ
TGR address
TGR
TGR read cycle
T
1
T
2
M
Internal
data bus
X M
Figure 10.49 Contention between TGR Read and Input Capture