Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 480 of 980
REJ09B0050-0600
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T
1
T
2
N M
TGR write data
TGR
N N + 1
Disabled
Figure 10.47 Contention between TGR Write and Compare Match
10.10.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T
2
state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 10.48 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T
1
T
2
N
TGR
N M
Buffer register write data
Figure 10.48 Contention between Buffer Register Write and Compare Match