Datasheet

Rev.6.00 Mar. 18, 2009 Page lii of lviii
REJ09B0050-0600
Section 6 Bus Controller (BSC)
Table 6.1
Pin Configuration ................................................................................................... 121
Table 6.2 Bus Specifications for Each Area (Basic Bus Interface)........................................ 147
Table 6.3 Data Buses Used and Valid Strobes ....................................................................... 152
Table 6.4 Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. 165
Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing.... 166
Table 6.6 DRAM Interface Pins............................................................................................. 167
Table 6.7 Idle Cycles in Mixed Accesses to Normal Space and DRAM ............................... 201
Table 6.8 Pin States in Idle Cycle .......................................................................................... 204
Table 6.9 Pin States in Bus Released State ............................................................................ 207
Section 7 DMA Controller (DMAC)
Table 7.1 Pin Configuration ................................................................................................... 215
Table 7.3 DMAC Activation Sources .................................................................................... 241
Table 7.4 DMAC Transfer Modes ......................................................................................... 244
Table 7.5 Register Functions in Sequential Mode.................................................................. 246
Table 7.6 Register Functions in Idle Mode ............................................................................ 249
Table 7.7 Register Functions in Repeat Mode ....................................................................... 252
Table 7.8 Register Functions in Single Address Mode .......................................................... 256
Table 7.9 Register Functions in Normal Mode ...................................................................... 259
Table 7.10 Register Functions in Block Transfer Mode........................................................... 262
Table 7.11 DMAC Channel Priority Order .............................................................................. 282
Table 7.12 Interrupt Sources and Priority Order ...................................................................... 287
Section 8 Data Transfer Controller (DTC)
Table 8.1
Relationship between Activation Sources and DTCER Clearing........................... 301
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs................ 304
Table 8.3 Chain Transfer Conditions ..................................................................................... 308
Table 8.4 Register Function in Normal Mode........................................................................ 308
Table 8.5 Register Function in Repeat Mode ......................................................................... 309
Table 8.6 Register Function in Block Transfer Mode ............................................................ 310
Table 8.7 DTC Execution Status............................................................................................ 314
Table 8.8 Number of States Required for Each Execution Status.......................................... 315
Section 9 I/O Ports
Table 9.1
Port Functions ........................................................................................................ 324
Table 9.2 MOS Input Pull-Up States (Port A)........................................................................ 372
Table 9.3 MOS Input Pull-Up States (Port B)........................................................................ 376
Table 9.4 MOS Input Pull-Up States (Port C)........................................................................ 380
Table 9.5 MOS Input Pull-Up States (Port D)........................................................................ 384