Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 479 of 980
REJ09B0050-0600
10.10.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T
2
state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 10.46 shows the timing in this case.
TCNT input
clock
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N M
TCNT write data
Figure 10.46 Contention between TCNT Write and Increment Operations
10.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T
2
state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 10.47 shows the timing in this case.