Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 478 of 980
REJ09B0050-0600
10.10.3 Caution on Cycle Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
f =
φ
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
10.10.4 Contention between TCNT Write and Clear Operations
If the counter clearing signal is generated in the T
2
state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed. Figure 10.45 shows the timing in this
case.
Counter clearing
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
N H'0000
Figure 10.45 Contention between TCNT Write and Clear Operations