Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 476 of 980
REJ09B0050-0600
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.42
shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status
flag clearing by the DTC or DMAC.
Status flag
Write signal
Address
TSR address
Interrupt
request
signal
TSR write cycle
T
1
T
2
φ
Figure 10.42 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
Address
Source address
DTC/DMAC
read cycle
T
1
T
2
Destination
address
T
1
T
2
DTC/DMAC
write cycle
φ
Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC* Activation