Datasheet

Rev.6.00 Mar. 18, 2009 Page l of lviii
REJ09B0050-0600
Figure 25.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1).............. 899
Figure 25.22 External Bus Release Timing ................................................................................. 900
Figure 25.23 External Bus Request Output Timing..................................................................... 900
Figure 25.24 DMAC Single Address Transfer Timing: Two-State Access................................. 902
Figure 25.25 DMAC Single Address Transfer Timing: Three-State Access............................... 903
Figure 25.26 DMAC TEND Output Timing ............................................................................... 903
Figure 25.27 DMAC DREQ Input Timing.................................................................................. 904
Figure 25.28 I/O Port Input/Output Timing................................................................................. 906
Figure 25.29 PPG Output Timing................................................................................................ 906
Figure 25.30 TPU Input/Output Timing...................................................................................... 906
Figure 25.31 TPU Clock Input Timing........................................................................................ 907
Figure 25.32 8-Bit Timer Output Timing .................................................................................... 907
Figure 25.33 8-Bit Timer Clock Input Timing ............................................................................ 907
Figure 25.34 8-Bit Timer Reset Input Timing............................................................................. 907
Figure 25.35 WDT Output Timing.............................................................................................. 908
Figure 25.36 SCK Clock Input Timing ....................................................................................... 908
Figure 25.37 SCI Input/Output Timing: Synchronous Mode ...................................................... 908
Figure 25.38 A/D Converter External Trigger Input Timing....................................................... 908
Figure 25.39 I
2
C Bus Interface Input/Output Timing (Option).................................................... 909
Appendix
Figure C.1 Package Dimensions (TFP-120)............................................................................. 950
Figure C.2 Package Dimensions (FP-128B) ............................................................................ 951
Figure D.1 Timing of Address Bus, RD, HWR, and LWR
(8-bit bus, 3-state access, no wait).......................................................................... 953