Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 425 of 980
REJ09B0050-0600
Table 10.21 TIORL_0
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function TIOCC0 Pin Function
0 0 0 0 Output disabled
1
Output
compare
register
*
Initial output is 0 output
0 output at compare match
1 0 Initial output is 0 output
1 output at compare match
1 Initial output is 0 output
Toggle output at compare match
1 0 0 Output disabled
1 Initial output is 1 output
0 output at compare match
1 0 Initial output is 1 output
1 output at compare match
1 Initial output is 1 output
Toggle output at compare match
1 0 0 0 Capture input source is TIOCC0 pin
Input capture at rising edge
1 Capture input source is TIOCC0 pin
Input capture at falling edge
1 ×
Input
capture
register
*
Capture input source is TIOCC0 pin
Input capture at both edges
1 × × Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Legend: ×: Don’t care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.