Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev.6.00 Mar. 18, 2009 Page 409 of 980
REJ09B0050-0600
Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)
Channel
Bit 7
CCLR2
Bit 6
CCLR1
Bit 5
CCLR0 Description
0, 3 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
*
1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input
capture
*
2
1 0 TCNT cleared by TGRD compare match/input
capture
*
2
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
*
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel
Bit 7
Reserved
*
2
Bit 6
CCLR1
Bit 5
CCLR0 Description
1, 2, 4, 5 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
*
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.