Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 398 of 980
REJ09B0050-0600
• PG4/CS4/BREQO
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
BRLE, bit BREQO, bit CS4E and bit PG4DDR.
EXPE
Operating
mode
7
1, 2, 4
1
1
1
1
1
0
1
0
−
−
−
−
−
−
−
−
−
0
0
0
1
0
0
1
0
1
0
0
1
0
1
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
BRLE
BREQ0E
CS4E
Pin
function
PG4
input
PG4
input
PG4
input
PG4
input
PG4
input
PG4
input
PG4
input
PG4
input
PG4
input
PG4
output
PG4
output
PG4
output
PG4
output
PG4
output
CS4
output
CS4
output
CS4
output
CS4
output
BREQO
output
BREQO
output
PG4
DDR
• PG3/CS3/RAS3, PG2/CS2/RAS2
The pin function is switched as shown below according to the operating mode, bit EXPE, bit
PGnDDR, bit CSnE, and bits RMTS2 to RMTS0.
Operating
mode
1, 2, 4 7
EXPE — 0 1
CSnE 0 1 — 0 1
RMTS2 to
RMTS0
— Area n is in
normal space
Area n is in
DRAM
space
— — Area n is in
normal space
Area n is in
DRAM
space
PGnDDR 0 1 0 1 — 0 1 0 1 0 1 —
Pin
function
PGn
input
PGn
output
PGn
input
CSn
output
RASn
output
PGn
input
PGn
output
PGn
input
PGn
output
PGn
input
CSn
output
RASn
output
Legend: n = 2 or 3