Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 395 of 980
REJ09B0050-0600
9.14 Port G
Port G is a 7-bit I/O port that also has other functions. The port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
• Port Function Control Register 0 (PFCR0)
9.14.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G.
PGDDR cannot be read; if it is, an undefined value will be read.
Bit Bit Name Initial Value R/W Description
7 — 0 — Reserved
6 PG6DDR 0 W
5 PG5DDR 0 W
4 PG4DDR 0 W
3 PG3DDR 0 W
2 PG2DDR 0 W
1 PG1DDR 0 W
0 PG0DDR 1/0
*
W
• Modes 1, 2, 4, and 7 (when EXPE = 1)
Pins PG6 and PG5 function as bus control
input/output pins (BREQ and BACK) when the
appropriate bus controller settings are made.
Otherwise, these pins are I/O ports, and their
functions can be switched with PGDDR. Pin PG4
functions as the bus control input/output pin
(BREQO) when the appropriate bus controller
settings are made. Otherwise, when the CS7E bit is
set to 1, pin PG4 functions as the CS7 output pin
when PG4DDR is set to 1, and as an input port
when the bit is cleared to 0. When the CS7E bit is
cleared to 0, pin PG4 is an I/O port, and its function
can be switched with PG4DDR. When the CS
output enable bits (CS3E to CS0E) are set to 1, pins
PG3 to PG0 function as CS output pins when the
corresponding PGDDR bit is set to 1, and as input
ports when the bit is cleared to 0. When CS3E to
CS0E are cleared to 0, pins PG3 to PG0 are I/O
ports, and their functions can be switched with
PGDDR.
• Mode 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Note: * PG0DDR is initialized to 1 in modes 1 and 2, and to 0 in modes 4 and 7.