Datasheet

Section 9 I/O Ports
Rev.6.00 Mar. 18, 2009 Page 393 of 980
REJ09B0050-0600
• PF2/CS6/LCAS
The pin function is switched as shown below according to the combination of the operating mode,
bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit
PF2DDR.
Operating
mode
1, 2, 4 3, 7
EXPE — 0 1
Areas 2 to 5 Any
DRAM
space
area is
16-bit
bus
space
All DRAM space areas are 8-
bit bus space, or areas 2 to 5
are all normal space
— Any
DRAM
space
area is
16-bit
bus
space
All DRAM space areas are 8-
bit bus space, or areas 2 to 5
are all normal space
CS6E — 1 0 — — 1 0
PF2DDR — 0 1 0 1 0 1 — 0 1 0 1
Pin function LCAS
output
PF2
input
CS6
output
PF2
input
PF2
output
PF2
input
PF2
output
LCAS
output
PF2
input
CS6
output
PF2
input
PF2
output
• PF1/CS5/UCAS
The pin function is switched as shown below according to the combination of the operating mode,
bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR.
Operating
mode
1, 2, 4 3, 7
EXPE — 0 1
Areas 2 to 5 Any
DRAM
space
area is
16-bit
bus
space
All DRAM space areas are 8-
bit bus space, or areas 2 to 5
are all normal space
— Any
DRAM
space
area is
16-bit
bus
space
All DRAM space areas are 8-
bit bus space, or areas 2 to 5
are all normal space
CS6E — 1 0 — — 1 0
PF1DDR — 0 1 0 1 0 1 — 0 1 0 1
Pin function UCAS
output
PF1
input
CS5
output
PF1
input
PF1
output
PF1
input
PF1
output
UCAS
output
PF1
input
CS5
output
PF1
input
PF1
output