Datasheet

Rev.6.00 Mar. 18, 2009 Page xliii of lviii
REJ09B0050-0600
Figure 7.30 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer.... 279
Figure 7.31 Example of DREQ Pin Low Level Activated Single Address Mode Transfer....... 280
Figure 7.32 Example of Dual Address Transfer Using Write Data Buffer Function................. 281
Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function .............. 282
Figure 7.34 Example of Multi-Channel Transfer ...................................................................... 283
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted
by NMI Interrupt .................................................................................................... 284
Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation...................... 285
Figure 7.37 Example of Procedure for Clearing Full Address Mode ........................................ 286
Figure 7.38 Block Diagram of Transfer End/Transfer Break Interrupt ..................................... 287
Figure 7.39 DMAC Register Update Timing ............................................................................ 288
Figure 7.40 Contention between DMAC Register Update and CPU Read................................ 289
Figure 7.41 Example in which Low Level is Not Output at TEND Pin .................................... 291
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC .......................................................................................... 294
Figure 8.2 Block Diagram of DTC Activation Source Control ............................................... 302
Figure 8.3 Correspondence between DTC Vector Address and Register Information ............ 303
Figure 8.4 Correspondence between DTC Vector Address and Register Information ............ 303
Figure 8.5 Flowchart of DTC Operation.................................................................................. 307
Figure 8.6 Memory Mapping in Normal Mode ....................................................................... 309
Figure 8.7 Memory Mapping in Repeat Mode ........................................................................ 310
Figure 8.8 Memory Mapping in Block Transfer Mode ........................................................... 311
Figure 8.9 Operation of Chain Transfer................................................................................... 312
Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)................... 313
Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2).............................................................................................. 313
Figure 8.12 DTC Operation Timing (Example of Chain Transfer) ........................................... 314
Figure 8.13 Chain Transfer when Counter = 0 .......................................................................... 319
Section 10 16-Bit Timer Pulse Unit (TPU)
Figure 10.1 Block Diagram of TPU........................................................................................... 404
Figure 10.2 Example of Counter Operation Setting Procedure ................................................. 439
Figure 10.3 Free-Running Counter Operation ........................................................................... 440
Figure 10.4 Periodic Counter Operation.................................................................................... 441
Figure 10.5 Example of Setting Procedure for Waveform Output by Compare Match............. 442
Figure 10.6 Example of 0 Output/1 Output Operation .............................................................. 443
Figure 10.7 Example of Toggle Output Operation .................................................................... 443
Figure 10.8 Example of Setting Procedure for Input Capture Operation................................... 444
Figure 10.9 Example of Input Capture Operation...................................................................... 445